ComfyUI-FeatherOps shows fp8 gains on RDNA3

This is a smart bandwidth-and-occupancy play, not a magic precision trick. The interesting part is that AMD users can squeeze more out of existing matrix hardware by changing where the data lives and how long it stays there.

• –The kernel keeps fp8 weights in LDS and upcasts late, which trims VRAM-to-LDS traffic and reduces instruction pressure in the K-loop.
• –The repo reports 52 TFLOPS in C++ and 43 TFLOPS in Python on Strix Halo, versus 30 TFLOPS for torch fp16, so the path can beat default ROCm kernels when overhead is controlled.
• –The author is explicit that bigger diffusion-sized matrices dilute the win, so this looks more compelling for smaller linear layers and batch-1 decode-like workloads.
• –It is handwritten HIP/asm rather than Triton or Tensile, which leaves headroom for deeper tuning but also means more sensitivity to ROCm and driver churn.