Ex-Google, Nvidia engineer drops AI chip blueprint

This document is an invaluable "peek behind the curtain" of high-level silicon design from an industry veteran who has worked on the world's most successful AI accelerators. It proposes a novel hardware design that diverges from both TPUs and GPUs, emphasizing hardware-software co-design. The blueprint offers a deep technical dive into systolic arrays, providing practical solutions for cell failure and manufacturing yield issues. Furthermore, it argues that AI hardware is fundamentally only as good as its compiler ecosystem, a common pitfall for hardware-first startups. The document provides a strategic roadmap for competing with incumbents by focusing on architectural efficiency and uncompressed performance, interleaving technical specifications with Silicon Valley "war stories" that provide essential industry context.