C++ book draft explores CPU physics

While developers spend hours tweaking compiler optimization flags, the real bottleneck remains the physical layout of data; utilizing linear memory structures to respect CPU caches and TLBs yields orders of magnitude more impact than micro-optimizing instruction flow.

* **Main Memory Bottleneck:** Accessing main RAM is roughly 100x slower than reading from L1 cache, making contiguous data structures like vectors essential.

* **The Illusion of Branch Hints:** Dynamic branch prediction hardware makes `[[likely]]`/`[[unlikely]]` attributes largely redundant except in rare, non-profiled edge cases or error-handling blocks.

* **Heap is Uncached:** Dynamic allocations must be treated as uncached unless accessed sequentially, emphasizing the need to minimize heap paging.

* **Physical Distance Rules:** Because parasitic capacitance scales with connection length, data placement relative to the CPU core is the single most critical factor in low-level performance.